1. Field of the Invention
The present invention generally relates to etching with high energy radiation or plasma, and more particularly, to a method and apparatus for controlling the etching rate at the edge of a wafer in an integrated semiconductor circuit manufacturing process.
2. Description of the Related Art
Since the mid-1960s, integrated semiconductor circuits have become the primary components of most electronics systems. These miniature electronic devices may contain thousands of the transistors and other circuits that make up the memory and logic subsystems of microcomputer central processing units. The low cost, high reliability, and speed of these computer chips has led them to become a ubiquitous feature of modern digital electronics.
The fabrication of an integrated circuit chip typically begins with a thin, polished slice of high-purity, single-crystal semiconductor material substrate (such as silicon or germanium) called a "wafer." Each wafer is subjected to a sequence of physical and chemical processing steps that form the various circuit structures on the wafer. During the fabrication process, various types of thin films may be deposited on the wafer using various techniques such as thermal oxidation to produce silicon dioxide films, chemical vapor deposition to produce silicon, silicon dioxide, and silicon nitride films, and sputtering to produce other metal films.
For example, U.S. Pat. Nos. 4,610,774 ("the '774 patent") and 4,724,060 ("the '060 patent") to Sakata et al. disclose a target for sputtering and a sputtering apparatus for use in integrated circuit manufacturing. FIG. 2 of the '774 patent illustrates a planar magnetron sputtering electrode device for forming a composite film on a substrate. The sputtering electrode has a projecting middle annular target member made of molybdenum, an outer annular target member made of silicon, and a disc-like inner target member which is also made of silicon. The middle target may also include an erosion member in the form of a V-shaped groove, W-shaped, rectangular shaped, or double rectangular shaped groove, as illustrated in FIGS. 1, 5, 6, and 7 of the '774 patent. FIG. 8 of the '774 patent illustrates another planar magnetron sputtering electrode including a wall provided at a circumferential position surrounding the outer silicon target member. It is disclosed that the wall may be maintained at the same, or lower, electric potential as the major surface of each target member in order to repulse and return electrons which tend to escape from the target area. As a result, the plasma density within the outer region can be increased in order to enhance the sputtering yield associated with an annular plasma at the outer position.
FIG. 1 of the '060 patent shows a planar magnetron sputtering apparatus including a target member having a plurality of recesses so that the sputtering particles are blocked by the side walls of the recesses whereby an even film may be deposited on a stepped substrate without forming any overhanging shapes on the substrate surface. The recesses may take on various shapes as illustrated in FIGS. 5-11 of the '060 patent.
After depositing a film on the semiconductor wafer, the unique electrical properties of semiconductors are produced by substituting selected impurities into the semiconductor crystal lattice using a process called doping. The doped silicon wafer may then be uniformly coated with a thin layer of photosensitive, or radiation sensitive, material called a "resist." Small geometric patterns defining the electron paths in the circuit may then be transferred onto the resist using a process known as lithography. During the lithographic process, the integrated circuit pattern may be drawn on a glass plate called a "mask" and then optically reduced, projected, and transferred onto the photosensitive coating covering the resist.
The lithographer resist pattern is then transferred onto the underlying crystalline surface of the semiconductor material through a process known as etching. Traditional etching processes employed wet chemicals that proved to be limited in terms of the size and aspect ratio (i.e., the height to width ratio of the resulting notch) of the features that could be formed on the wafer. Consequently, the number of circuits that could be packed onto a single wet-etched wafer, and hence the ultimate size of the electronic device, were limited by traditional chemical etching processes.
Dry plasma etching, reactive ion etching, and ion milling techniques were later developed in order to overcome the limitations associated with chemical etching. Plasma etching, in particular, allows the vertical etch rate to be made much greater than the horizontal etch rate so that the resulting aspect ratio of the etched features can be adequately controlled. In fact, plasma etching enables very fine features with high aspect ratios to be formed in films approaching 1 micrometer in thickness.
During the plasma etching process, a plasma is formed above the masked surface of the wafer by adding large amounts of energy to a gas at low pressure. This is commonly accomplished by creating electrical discharges in gases at about 0.001 atmospheres. The resulting plasma may contain ions, free radicals, and neutral species with high kinetic energies. By adjusting the electrical potential of the substrate to be etched, the charged particles in the plasma can be directed to impinge upon the unmasked regions of the wafer and thereby knock out atoms in the substrate.
The etching process can often be made more effective by using gases that are chemically reactive with the material being etched. So called "reactive ion etching" combines the energetic etching effects of the plasma with the chemical etching effect of the gas. However, many chemically active agents have been found to cause excessive electrode wear.
It is desirable to evenly distribute the plasma over the surface of the wafer in order to obtain uniform etching rates over the entire surface of the wafer. For example, U.S. Pat. Nos. 4,792,378 and 4,820,371 to Rose et al. disclose a shower head electrode for distributing gas through a number of holes in the electrode. These patents generally describe a gas dispersion disk having an arrangement of apertures which is tailored to the particular pressure gradients existing within a reactor chamber in order to provide a uniform flow of gas vapors to a semiconductor wafer. The gas dispersion disk is intended to function as a selective barrier to counteract gradient pressures below the disk and to provide a uniform flow through the shower head electrode for distribution over the entire surface of the wafer.
Since the integrated circuit fabrication process is quite sensitive to both particulate and impurity contamination, even airborne particulate matter as small as 1 micrometer must be prevented from contacting the surface of the wafer during the etching process. Consequently, it is often desirable to confine the plasma to the area which is immediately over and around the wafer substrate. However, physically confining the plasma in this manner has been found to cause reduced plasma densities at the edges of the plasma discharge, thus reducing etching rates near the edges of the wafer. For example, the '774 patent discloses an annular wall around a sputtering target that can repulse, and return toward the center, those electrons which tend to escape from the plasma during the sputtering process. Any discontinuities or irregularities in the plasma discharge system, such as pumping ports, may also affect the density of the plasma being discharged.
Conventional attempts to uniformly distribute confined plasmas, or to redistribute the plasma near the edges of the electrode, have been found to cause other undesirable changes in etching process parameters such as etch selectivity and etch profile. Furthermore, even after optimizing process variables such as pressure, power, and gas flow, it is often impossible compensate for this edge effect without adversely affecting other process variables. Therefore, there is a significant need in the art to control the plasma density, especially near the edges of a plasma discharge, without upsetting other process parameters such as etch selectivity and etch profile.